Kleinosowski Scholarship Essay


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Nano, Quantum and Molecular Computing Implications to High Level Design and Validation Edited by

Sandeep K. Shukla Virginia Polytechnic and State University, Blacksburg, U.S.A. and

R. Iris Bahar Brown University, Providence, U.S.A.


eBook ISBN: Print ISBN:

1-4020-8068-9 1-4020-8067-0

©2004 Springer Science + Business Media, Inc. Print ©2004 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America

Visit Springer's eBookstore at: and the Springer Global Website Online at:

http://www.ebooks.kluweronline.com http://www.springeronline.com

Sandeep dedicates this book to his mother Atashi, grandmother Nirupama, and brother Rajiv. Iris dedicates this book to her husband Andrew and daughters Jasmine and Maya, who provide endless support even with her crazy work schedule.

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Dedication Preface Foreword Acknowledgments Part I Nano-Computing at the Physical Layer Preface

v xi xv xvii


1 Nanometer Scale Technologies: Device Considerations Arijit Raychowdhury and Kaushik Roy 1.1. Introduction 1.2. Silicon Nanoelectronics 1.3. Carbon Nanotube Electronics 1.4. Molecular Diodes and Switches 1.5. Conclusion References

5 6 11 27 29 29

Part II Defect Tolerant Nano-Computing Preface


2 Nanocomputing in the Presence of Defects and Faults: A Survey Paul Graham and Maya Gokhale 2.1. Background 2.2. Error Detection, Masking, and Reconfiguration 2.3. Non-Traditional Computing Models and Architectures 2.4. Tools 2.5. Summary References 3 Defect Tolerance at the End of the Roadmap Mahim Mishra and Seth C. Goldstein 3.1. Approaches for Achieving Defect Tolerance in the Nanometer Domain


39 40 42 58 64 66 67 73 76


NANO, QUANTUM AND MOLECULAR COMPUTING 3.2. Technology 3.3. Toolflow Required to Achieve Defect Tolerance 3.4. Testing 3.5. Placement and Routing 3.6. Summary 3.7. Acknowledgments References

4 Obtaining Quadrillion-Transistor Logic Systems Despite Imperfect Manufacture, Hardware Failure, and Incomplete System Specification Lisa J. K. Durbeck and Nicholas J. Macias 4.1. Four Areas for New Research 4.2. Cell Matrix Overview 4.3. Example of Future Problems: Lower Reliability 4.4. Summary, Conclusions References 5 A Probabilistic-based Design for Nanoscale Computation R. Iris Bahar, Jie Chen, and Joseph Mundy 5.1. Introduction 5.2. MRF Design for Structural-based Faults 5.3. Design for Signal-based Errors 5.4. Future Directions 5.5. Acknowledgments References 6 Evaluating Reliability Trade-offs for Nano-Architectures Debayan Bhaduri and Sandeep K. Shukla 6.1. Introduction 6.2. Background 6.3. Analytical Approaches for Reliability Analysis 6.4. NANOLAB: A MATLAB Based Tool 6.5. Reliability Analysis of Boolean Networks with NANOLAB 6.6. NANOPRISM: A Tool Based on Probabilistic Model Checking 6.7. Reliability Analysis of Logic Circuits with NANOPRISM 6.8. Reliability Evaluation of Multiplexing Based Majority Systems 6.9. Conclusion and Future Work 6.10. Acknowledgments References 7 Law of Large Numbers System Design Andr´e DeHon 7.1. Introduction 7.2. Background

78 82 85 100 103 104 104 109 110 115 120 130 131 133 133 136 149 153 155 155 157 158 162 173 178 183 191 194 199 205 207 207 213 213 215

Contents 7.3. “Law of Large Numbers” Above the Device Level 7.4. Component and System Level LLN in Conventional Systems 7.5. Architectures with Sparing 7.6. Architectures with Choice 7.7. Unique Nanoscale Addressing via Statistical Differentiation 7.8. Generalizing Statistical Assembly 7.9. Fault Tolerance 7.10. Atomic-Scale System Stack 7.11. Summary 7.12. Acknowledgments References Part III Nano-Scale Quantum Computing Preface 8 Challenges in Reliable Quantum Computing Diana Franklin and Frederic T. Chong 8.1. Quantum Computation 8.2. Error correction 8.3. Quantum Computing Technologies 8.4. Fabrication and Test Challenges 8.5. Architectural Challenges 8.6. Conclusions 8.7. Acknowledgements References 9 Origins and Motivations for Design Rules in QCA Michael T. Niemier and Peter M. Kogge 9.1. The Basic Device and Circuit Elements 9.2. Implementable QCA 9.3. Design Rules 9.4. Wrap up References 10 Partitioning and Placement for Buildable QCA Circuits Sung Kyu Lim and Mike Niemier 10.1. Preliminaries 10.2. Problem Formulation 10.3. Zone Partitioning Algorithm 10.4. Zone Placement Algorithm 10.5. Cell Placement Algorithm 10.6. Experimental Results 10.7. Conclusions and Ongoing Work References

ix 216 217 218 222 226 227 237 237 237 238 238

245 247 249 253 256 258 260 263 264 264 267 268 279 283 292 292 295 296 300 303 306 308 313 316 316



Part IV Validation of Nano-Scale Architectures Preface 11 Verification of Large Scale Nano Systems with Unreliable Nano Devices Michael S. Hsiao, Shuo Sheng, Rajat Arora, Ankur Jain and Vamsi Boppana 11.1. Introduction 11.2. Scalable Verification of Nano Systems 11.3. Scalable Unbounded Model Checking 11.4. Scalable Bounded Model Checking 11.5. Verification in the Presence of Unknowns and Uncertainties 11.6. Summary 11.7. Acknowledgments References Biographies

321 323 324 325 326 338 344 347 348 348 352


...no one expects conventional silicon-based micro-electronics to continue following Moore’s Law forever. At some point, chip-fabrication specialists will find it economically infeasible to continue scaling down microelectronics. As they pack more transistors onto a chip, phenomena such as stray signals on the chip, the need to dissipate the heat from many closely packed devices, and the difficulty of creating the devices in the first place will halt or severely slow progress.

The above quotation is taken from an essay titled “Computing with Molecules” written by Mark Reed and James Tour in 2002. The quote clearly shows that as computer engineers we are at a technological and scientific inflection point. However, the advent of nanotechnology might be the recourse for continuing improvement of our computing power. Computer engineers and scientists face new challenges as nano-technological innovations grow in different fields of science and technology. As industry experts argue on the scaling of Moore’s law beyond 2015, one fact is certain about the future of electronics: The certainty is in the uncertainty germane in the size, nature, and physics of electronic devices on which we will build our future computing and communications infrastructures. One of the grand challenges in the nano-scopic computing era is guarantees of robustness. Robust computing system design is confronted with quantum physical, probabilistic, and even biological phenomena, and guaranteeing high reliability is much more difficult than ever before. Scaling devices down to the level of single electron operation will bring forth new challenges due to probabilistic effects and uncertainty in guaranteeing ‘zero-one’ based computing. Minuscule devices imply billions of devices on a single chip, which may help mitigate the challenge of uncertainty by replication and redundancy. However, such device densities will create a design and validation nightmare with the shear scale. Much of the nanotechnology research taking place today is confined in the domain of material science, electrical engineering, quantum and device physics, chemistry, and even biology. However, computer engineers and scientists will be forced to confront the effects that we described above as nanostructured



material with unreliable and defective substrates begin to enter into the main stream of computer design. According to estimates made by nanotechnology experts, we should see such substrates in the upcoming years (see Table 0.1), and hence the associated problems of guaranteeing reliable computing and scaling in design automation tools. This table, published in Wired Magazine about 10 years ago, might not reflect the current predictions. Nonetheless, a point to remember about this table is that breakthroughs in nanotechnology are happening every day and hence predictions of this nature are being updated accordingly. As an example, last April at a conference in Washington DC, a company announced that they have been able to capture images at 10−8 meter scale, which is a breakthrough in the capability of Scanning Tunneling Microscopes. Such inventions often lead to a quick progression unprecedented and heretofore unthinkable. Table 0.1. Prediction on Arrival of Nano Computing by Nano Technology Experts, Wired Magazine in 1995 Expert Name Arrival Prediction

Birge 2005

Brenner 2025

Drexler 2015

Hall 2010

Smalley 2100

The questions that confront computer engineers regarding the current status of nanocomputing material and the reliability of systems built from such miniscule devices, are difficult to articulate and answer. We have found a lack of resources in the confines of a single volume that at least partially attempts to answer these questions. In November 2003, during the International Conference on Computer-Aided Design (ICCAD) we started a discussion with Mark De Jhong of Kluwer on the idea of putting together a book that would serve as a single source for addressing many of the questions researchers would confront when designing systems based on nano-scale or quantum effect devices. Fortunately, that year, following ICCAD in San Jose, the IEEE High Level Design and Validation Workshop (HLDVT) was held in San Francisco. At the workshop, we organized a special session entitled “Science of The Small Coming the Bigway: Are We Ready for the Design and Validation Challenges?” The speakers included Seth C. Goldstein, Forrest Brewer, and Sankar Basu. Seth Goldstein spoke about his work on defect-tolerant, dynamically reconfigurable architectures that are based on future molecular devices, which drew much interest from the audience. Forrest Brewer talked about coherence effects in today’s computing, and how the future computing paradigms need to preserve some of these coherence effects. Finally, Sankar Basu from the National Science Foundation spoke about important issues in nanocomputing and the NSF’s interest in nanotechnology. A very interesting panel discussion followed, and from the discussions and queries



from the audience, we were more convinced that we need a single source put together for bringing these issues to the forefront. This resulted in our effort to collect some of the most relevant work that deals with the issue of design and validation of architectures on top of nano-scale devices. As we discussed the possibility of this edited book with the experts in the field, they were immediately ready to help out by contributing various chapters. Their immediate response and enthusiam has made this very informative volume possible, within a span of six months. Based on the emphasis of the chapters, we have divided the book into four major parts. The first part is meant to introduce the readers to the physical realities of implementing nano-computing, using various technologies such as carbon nano tubes (CNT), quantum dots, and molecular switches. This part also ties in physical layer design issues such as variational effects. The sole chapter in this part is written by Arijit RoyChowdhury and Kaushik Roy from Purdue University. In this opening chapter they introduce the readers to the intricacies as well as the promises of the nano-scopic technologies for implementing computing. Part two is a relatively larger part of this volume, and mainly focuses on defect-tolerance. As we have hinted earlier, defects will be a feature of nanotechnology by the estimates by experts. One can no longer assume that pieces of silicon that pass the post-silicon tests are the only one used for system design. As a result, designers and system architects have to consider defect-tolerance as a first-order parameter when making design decisions. These defects are not only due to manufacturing imperfection, but also due to signal noise, quantum effects, deformation, and aging. Techniques from traditional fault-tolerant literatures need to be borrowed and enhanced, reconfigurability needs to be designed in, and reliability figures of merits need to be computed. The six chapters in part II are dedicated to this important aspect of nano-computing. This part starts with an article by Paul Graham and Maya Gokhale of Los Alamos Labs, where various defect-tolerant techniques are surveyed. Given this introduction, the next chapter by Mahim Mishra and Seth Goldstein discusses reconfiguration centric defect-tolerance. The next chapter written by Lisa Durbeck and Nicholas Macias of Cell Matrix, introduces more abstract reconfigurable fabric implementation in the form of cells, which will allow dynamic reconfiguration for localization of defects, and thereby guarantee fault-containment. After the readers have thorougly familiarized themselves with reconfiguration based defect tolerance in the first three chapters, the following chapter by Iris Bahar, Jie Chen and Joseph Mundy of Brown University presents a novel model of computation to capture the coherence effects in nanocomputing devices, and how Markov Random Fields can be used to capture the computing with such effects. This chapter is a great introduction to the next chapter by Debayan Bhaduri and Sandeep Shukla of Virginia Polytechnic on automated tools for reliability/redundancy trade-offs for defect-tolerant architectures. The final pa-



per in this part is by Andr´e DeHon from Caltech, titled “Law of Large Numbers for System Design” which brings perspective to the uncertainty at the device level in the nanoscopic substrate and where the abstraction boundaries are, and at what levels we assume determinism approximating the uncertainties. One very important technology for nano-scale computing is projected to be Quantum Dot Cellular automata and variants of quantum computing devices. Given that such devices work with single electron quantum dots, and the computation often blurs the demarkation between 1 and 0s, implications to high level design when using these technologies may be quite broad. Part three of this book is organized in three chapters dealing with quantum dot devices and their design parameters and rules. The first chapter is a great introduction to the challenges of Quantum Computation by Diana Franklin of California Polytechnic State University, and Fred Chong of University of California at Davis. This opening chapter is followed by two chapters dealing with design rules of QCA devices. The first one by Michael Niemier of Georgia Tech and Peter Kogge of the University of Notre Dame provides a detailed look at the Quantum Dots, Quantum Wires, and clocking issues. The second one by Sung Kyu Lim and Michael Niemier from Georgia Tech follows on this to discuss clock zoning in such systems and details the algorithms for partitioning systems into clock zones. These papers will be of great importance to design automation tool designers for future QCA based systems. Part four complements the rest of the chapters with a single chapter on a look at formal verification technology for large scale designs and for designs with unknowns or uncertainties. This last chapter is written by Michael Hsiao and Rajat Arora of Virginia Tech, Shuo Sheng of Mentor Graphics, Ankur Jain from University of California at Berkeley, and Vamsi Boppana of Zenasis. This part introduces to the readers possibilities of verifying large scale designs with redundancy and replications as we have seen common in defect-tolerant design. In summary, we believe that this volume contains a large amount of research material as well as new ideas that will be very useful for some one starting research in the arena of nanocomputing, not at the device level, but addressing the problems one would face at system level design and validation when nanoscopic physicality will be present at the device level. Sandeep K. Shukla and R. Iris Bahar


The manufacturing approaches that have been developed and evolved for modern computational hardware represent what is undoubtedly the highest level of technological achievement that the world has ever witnessed. For some 30+ years this technology has advanced at a pace and through a number of generations that is unsurpassed by any other. However, it has also become increasingly apparent that over the next decade, this technology paradigm will mature. Issues such as power consumption, lithographic patterning limitations, and others are beginning to come up as red flags. Nevertheless, the physics of computation is still young. A number of emerging approaches, each one of which represents, to some degree, a paradigm shift, are beginning to gain at least scientific credibility. These approaches include quantum computation, spintronics, quantum cellular automata (QCA), molecular electronics and neural networks, to name just the major ones. All of these approaches have so-called ‘killer applications’. For quantum computing, it is the reduced scaling of various classes of NP-hard problems. For QCA it is an energy efficient computational approach that should get better as the components are reduced in size. For spintronics, it is a memory density that scales exponentially with the number of coupled spin transistors. For molecular electronics, it is an improved energy efficiency per bit operation as well as the potential for continued device scaling to true molecular dimensions. True neural networks possess a greatly increased connectivity and therefore the potential for a greatly increased rate of information flow through a circuit. All of these alternative computing approaches face tremendous challenges that must be overcome before they can transition into technologies. These include, for example, issues related to materials and/or molecular components that are completely foreign to modern electronics manufacturing. Furthermore, most of them are nanotechnologies — that is, they will require a near atomic level control over the manufacturing steps, and manufacturing ‘noise’ will translate directly into defective components. Finally, each of them will require new thinking and significant breakthroughs with respect to architecture. This last point is a critical one. Just as it is foolish to build a house without appropriate design guidelines, it is foolish to build a new computational technology



without co-designing a framework for that construction. This emerging arena of ‘alternative computer architectures’ constitutes a new branch of computer engineering that is both fraught with challenges and rich with opportunity. This book will serve a unique purpose. Several times over the past few years I have had students ask me to point them toward literature references on defect tolerant architectures for nano-electronics, or nanoelectronics design concepts, etc. For quantum computing and neural nets, well established research communities exist and such references are easy to point to. For some of these other paradigms, papers often appear in journals that biologists, chemists, materials scientists, physicists, etc., rarely encounter — or, worse yet — students must turn to patent literature! This book brings together, for the first time, many of these modern architectural concepts into a single text, with chapters written by a terrific group of experts. It is sure to become a mainstay in my group, and I expect that it will be a valuable resource for many years to come. Jim Heath Elizabeth W. Gilloon Professor California Institute of Technology


The editors would like to thank the following people and agencies for helping make this book become a reality. First, we would like to thank Sankar Basu from the National Science Foundation for his initial encouragement and support behind this book. In addition, we would like to acknowledge the NSF for providing support for our own nanotechnology research under grant numbers CCR-0340740 and CCR-0304284. We would also like to thank Mark De Jongh from Kluwer Academic Publishers for working with us and helping to ensure a fast turnaround time for the book. We also thank Cindy Zitter from Kluwer, for all her timely help with administrative issues. We are grateful to Jim Heath, the Elizabeth W. Gilloon Professor of Chemistry at California Institute of Technology, for encouraging the project with his foreword for the book. We would also thank the authors of the different chapters in this book for their patience and timely production of the chapters. We thank Forrest Brewer for his encouragement at the inception of this project. Lisa Durbeck has also helped us in planning some of the topic areas. The students of FERMAT Lab at Virginia Tech, especially Hiren D. Patel and Debayan Bhaduri have helped with a lot of LaTex issues, and with reviewing some of the chapters. We thank them for their help and dedication. Finally, we would like to thank Nikil Mehta for the countless hours he devoted to helping us format and compile this book. His great attitude and resourcefulness made him a pleasure to work with. He’s more of a LaTex wizard than he gives himself credit for.

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Feymann said in one of his famous lectures “There is plenty of room at the bottom,” in which he referred to the possibility that computing advances may not have to stop with the gradually diminishing stature of Moore’s Law for silicon technologies. New possibilities are abundant when we can harness the computing powers inherent in miniscule particles, atoms, molecules, and their Coulombic, van der Waals, and quantum interactions, which so far have gone unexploited. In a way, silicon technology is already at the threshold of nano-technological wonders. At the time of publishing this book, most semiconductor companies have been manufacturing devices at the 90nm scale, some going to 65 nanometer. Companies have even figured out how to scale below these numbers. However, with device scaling, comes a plethora of problems related to reliability in the face of cosmic particles, quantum physical interactions, and other physical phenomena which did not play such an important role in the recent past. As we scale down in size, we also scale up in number. This throws a challenge as well for the designers of tools that need to simulate, validate and compute various performance measures for systems built on nano-scale technologies. The International Technology Roadmap has projected that silicon technology could easily continue scaling down at least until the middle of the next decade. To continue beyond this point, we have to think of alternative technologies. Already we have been seeing some such alternatives in the form of Carbon Nanotube devices, molecular switches, and Quantum Dot cellular automata to name a few. These not only provide novel challenges to the technologists who physically try to make them but also to designers of systems who have so far assumed perfect or near perfect non-linear devices as basic components of their systems. These new technologies not only bring forth new physical challenges, but also imply system level challenges, where the probabilistic nature of devices become a reality, and a first class parameter for high level design. Parts II, III, and IV of this book discuss issues pertaining to system level design based on nano-scopic technologies. However, in this first part, in order to ground ourselves to physical reality, we present a chapter that discusses both the scaling issues in silicon based technologies in the nano-era, as well as carbon 3 S.K. Shukla and R.I. Bahar (eds.), Nano, Quantum and Molecular Computing, 3-4. © 2004 Kluwer Academic Publishers. Printed in the Netherlands.



nanotube (CNT) based technology issues at the physical layer. We believe this chapter will provide the readers with the appropriate background to appreciate the later chapters.

Chapter 1 NANOMETER SCALE TECHNOLOGIES: DEVICE CONSIDERATIONS Arijit Raychowdhury Department of Electrical and Computer Engineering Purdue University IN, USA [email protected]

Kaushik Roy Department of Electrical and Computer Engineering Purdue University IN, USA [email protected]


This chapter discusses the problems and challenges in scaling Silicon transistors in the nanotechnology era. The principle bottle necks to the scaling of Silicon devices have been discussed. In the latter half of this chapter, novel devices, particularly carbon nanotubes, have been introduced as possible alternatives to Silicon. The material properties, principal device characteristics and circuit issues relating to these revolutionary devices have been discussed.


Keywords: Scaling of Silicon, Leakage current, Process variation, Molecular transistors, Carbon Nanotubes.



For the last three decades the semiconductor industry has witnessed an exponential growth in accordance with Moore’s Law. Integration density has attained incredible heights and on-chip functionality has advanced from simple adders to systems-on-chip in the same time frame. Challenges in device design, circuit engineering, and fabrication have been met and overcome. As we advance to an era of nanotechnology, the promise is enormous. Wearable 5 S.K. Shukla and R.I. Bahar (eds.), Nano, Quantum and Molecular Computing, 5-33. © 2004 Kluwer Academic Publishers. Printed in the Netherlands.



computers, bio sensors, adaptive control systems are all set to have a large impact on life. In this new era, the semiconductor devices will be scaled down to their physical limits. In the process, the circuit and the system engineer is faced with the challenges of scaling. The Silicon MOSFET is no longer a perfect switch and the ratio of the on current to the off current is decreasing [14, 43, 57, 21]. Further, process variation has led to variation of the critical transistor parameters like length, width and threshold voltage (Vth ) thereby reducing the production yield. Research has started in the earnest to gauge the possibility of newer device structures to mitigate these problems. The novel devices include modifications of bulk silicon into FINFETs, trigate structures, and double gate MOSFETs [55]. For example, these modified MOSFETs have better short channel immunity and better subthreshold slopes. Device designers are also looking at revolutionary devices like carbon nanotube transistors, molecular diodes and nano electromechanical systems. These devices with characteristics different from Silicon could potentially have better scalability and increase the on current to off current ratio. In this chapter, a brief overview will be presented on the issues associated with super-scaled bulk silicon devices and an introduction to non-silicon alternatives will be put forward. Carbon nanotubes have emerged as the most promising alternative device in the nanotechnology era and there has been considerable interest in the design and understanding of carbon nanotube field-effect transistors. In the second part of this chapter, the nature and properties of carbon nanotubes and carbon nanotube field-effect transistors will be discussed from a circuit designer’s point of view.


Silicon Nanoelectronics

To achieve higher density and performance at lower power consumption, MOS devices have been scaled for more than 30 years [48], [6], [1]. Transistor delay times have decreased by more than 30% per technology generation resulting in doubling of microprocessor performance every two years. Supply voltage (VDD) has been scaling down at the rate of 30% per technology generation in order to keep power consumption under control. Hence, the transistor threshold voltage (Vth ) has to be commensurately scaled to maintain high drive current and achieve performance improvement of at least 30% per technology generation. The semiconductor industry has enjoyed the fruits of scaling; but with shorter and shorter devices the problems of scaling are becoming more and more predominant. In the first section of this chapter we would visit some of the scaling issues of bulk silicon transistors.

Nanometer Scale Technologies: Device Considerations


Short Channel Effects Short channel effect in scaled MOSFET devices is the lowering of the threshold voltage Vth with decreasing channel length [55]. In long-channel devices, the source and drain are separated far enough that their depletion regions have no effect on the potential or field pattern in most part of the device, and hence, the threshold voltage is virtually independent of the channel length and drain bias. In a short-channel device, however, the source and drain depletion width in the vertical direction is comparable to the effective channel length. This causes the depletion regions from the source and the drain to interact with each other. The obvious consequence of this is lowering of the potential barrier between the source and the channel. This causes lowering of the threshold voltage of the MOSFET with decreasing channel length, a phenomenon referred to as short channel effect [55, 40, 51]. Figure 1.1 illustrates the effect of channel length scaling on the surface potential of the device along the length. Apart from the channel length, the drain voltage also has a significant effect on the potential barrier for short channel devices. Under off conditions, this potential barrier between the source and the channel prevents electrons from flowing to the drain. For a long-channel device, the barrier height is mainly controlled by the gate voltage and is not sensitive to Vds . However when a high drain voltage is applied to a short-channel device, barrier height is lowered resulting in further decrease of the threshold voltage. The source then injects carriers into the channel surface without the gate playing a role. This is known as drain induced barrier lowering (DIBL). DIBL is enhanced at higher drain voltage and shorter effective lengths Surface DIBL typically happens before deep bulk punch through. Ideally, DIBL does not change the subthreshold slope, S, but does lower Vth . The DIBL effect increases as Vds increases. Higher surface and channel doping and shallow source/drain junction depths reduce the DIBL effect [55, 40, 51]. In scaled Silicon MOSFETs several other effects like Gate induced drain leakage (GIDL), hot electron effect and punch-through are important for different biasing regions [55].

Leakage Current in Scaled Devices It has already been established that one of the primary concerns in Silicon MOSFETs is the increasing drain control over the channel. Figure 1.2 illustrates how leakage power is fast catching up with active power in scaled CMOS and Figure 1.2 shows the principle leakage current components in scaled Silicon devices. As DIBL increases, the Vth of the device gets significantly lowered resulting in higher subthreshold leakage current. Subthreshold or weak inversion current is the drain current of the MOSFET when the gate is biased voltage less than Vth . The minority carrier in the weak inversion region is small but



Figure 1.1. Surface potential versus lateral distance (normalized to the channel length L) from the source to the drain for (a) long-channel MOSFET (L = 6.25µm, Vds = 0.5V ), (b) a short-channel MOSFET (L = 1.25µm, Vds = 0.5V ), (c) a short channel MOSFET at high drain bias (L = 1.25µm, Vds = 5V ). The gate voltage is same for all three cases [55].

not zero. This results in a diffusion current from the drain to the source of the device even when the gate to source voltage (Vgs ) is at zero potential. The current increases exponentially as the threshold voltage is lowered [55, 51]. To mitigate the problem of lowered Vth in MOSFETs, the channel doping is increased in a region below the drain and the source (retrograde well) and near the source-bulk and drain-bulk junctions (halo implants) [15] (refer to Figure 1.3). These higher doping regions serve to increase the threshold voltage of the device and lower the subthreshold current. However, for scaled devices (lef f < 50nm) the increased halo doping creates a high electric field across the reverse biased drain-bulk junction. This causes a junction band-to-band tunneling (BTBT) current to flow from the drain to the source of an n-MOS device. A similar current flows across the source-body junction too depending on the biasing conditions. Thus the halo doping decreases the subthreshold current at the cost of higher BTBT leakage in scaled devices. Figure 1.3 illustrates how the subthreshold and the BTBT currents vary with increasing halo doping. For scaled devices the oxide thickness is scaled commensurately to increase the gate control over the channel [51]. This has resulted in yet another significant leakage current called gate tunneling leakage [20, 9, 29, 60]. Gate tunneling current is the current due to tunneling of electrons from the conduction band of bulk silicon and the source/ drain overlap regions through the potential barrier of the oxide into the gate of the device. This tunneling current becomes more significant as the oxide thickness is scaled and for sub-100nm devices where the oxide thickness is about or below 20ºA, gate tunneling forms an important

Nanometer Scale Technologies: Device Considerations


Figure 1.2. (a) Increase in leakage current with technology scaling (Source: Intel) (b) The different components of leakage in scaled technologies.

(a) Figure 1.3. Typical channel profile showing the retrograde well and the halo regions. (b) The variation of the different leakage components with increasing halo doping.

leakage component. Simulation results from a super scaled device (lef f ∼ 25nm), (Figure 1.3) show the contribution of different leakage components. In scaled Silicon devices, the leakage current increases almost exponentially with scaling. This reduces the on current to off current ratio of transistors and also consume considerable amount of power even in the standby mode. In order to alleviate the leakage power consumption in densely integrated logic and memory designs, circuit engineers and researchers have proposed different schemes. One of the popular methods to reduce leakage power is to use multiple Vth transistors in the design, where the performance critical transistors are allowed to have a lower Vth whereas the Vth of the off-critical transistors are set at a higher value. This can be implemented using multiple channel dopings [56,



58, 55, 33, 11, 24], multiple oxide thicknesses (MOXCMOS), multiple Channel Lengths [51] and multiple Body Bias techniques [22]. Further the use of transistor stacks has been proposed to reduce subthreshold leakage in the standby mode [22, 52, 45]. In certain circuit applications, the whole circuit is forced to a low Vdd (or drowsy) state in the standby mode thereby causing significant reduction in leakage power[51]. Another popular technique is to adaptively control the threshold voltage during various operation modes to reduce the overall leakage power without degrading the performance [11]. These design techniques [22] are finding their ways in the mainstream design methodology for ultra high performance and low power processors.

Process Variation Process parameter variation has also been identified as one of the principle bottlenecks in scaling of Silicon MOSFETs beyond 100nm [46, 5, 19]. As the device dimensions continue to shrink, it is becoming increasingly difficult to control the critical process parameters, like gate length, oxide thickness and dopant concentration. To add to this is the random dopant fluctuation [55]. This has resulted in significant variation of the threshold voltage of the device thereby causing a considerable spread in the switching delay of the logic gates. Die-to-die process variation causes the all the transistors in a particular die to have a mean Vth that may be different from the nominal (refer to Figure 1.4). On the other hand the within-die variation increases the spread (or variance) of the Vth in a single die thereby affecting transistor matching and delay spread adversely [19, 53, 17]. While process variation causes significant change in the performance, its impact on transistor leakage is even more [5]. Figure 1.4 illustrates, a 2X variation in the ‘ON’ current of the device corresponds to 100X variation in the leakage current. The increase in leakage current and process variation in scaled Silicon devices may prove to be showstoppers. Even in circuits with low activity (for example, level 2 caches) the increase in leakage power has led to high power consumption thereby reducing battery lifetime. With process variation production yield has gone down drastically and new design methodologies like statistical timing analysis, statistical sizing for yield are becoming popular. In the regime where the gate lengths are scaled below 50nm, predictable circuit design with tolerable power budgets may become uneconomical for production [54]. Hence, leading researchers are investigating modified device structures like FINFETs, partially depleted SOI and double gate MOSFETS [55]. A discussion on these modified device structures is beyond the scope of this chapter. If Silicon electronics reach the limits of scalability, it will only be prudent to look for other materials to replace Silicon. Carbon nanotube has emerged as a promising replacement to Silicon in future nanoelectronic designs. In the following sections we will give an overview of the non-Silicon


Nanometer Scale Technologies: Device Considerations



Figure 1.4. (a) Variation of Vth for scaled technologies [14]. (b) The variation of the ON and OFF currents with process variation.

based molecular devices such as carbon nanotubes and molecular diodes which show promise for the future. Carbon nanotube transistors are predicted to have about ten times the current density of silicon MOSFETs and maintain an on-current ot off-current ratio of more than 103 . Further, carbon nanotubes will allow successful integration of high κ gate dielectrics because there is no dangling bond in carbon nanotubes. This would result in the possible use of thicker gate dielectrics thereby reducing gate leakage at no performance penalty. Several other molecular diodes that are being currently investigated show enormous promise as ultra-scaled switches for future technologies.


Carbon Nanotube Electronics

In a pursuit for novel materials in a post Silicon electronics era, scientists and engineers worldwide have already started active research in carbon nanotube electronics[16, 4, 32]. Although carbon filaments of nanoscaled diameters (∼10nm ) were extensively grown in the ‘70s and the ‘80s, it was only after the pioneering work of Iijima in 1991 [31] that the potential of carbon nanotube as a possible device material has been recognized and extensively studied. Owing to their excellent electrical, mechanical and thermal properties, researchers have identified an array of potential applications for carbon nanotubes. Even in a the short span since their inception, field effect transistors, diodes, optical and cathode ray emitters, bio-sensors and energy storage elements have been demonstrated [16]. Carbon nanotube (CNT) electronics is still in its infancy and the transport, contacts, interfaces and electrostatics of these devices require detailed understanding. Experimentalists and theoreticians have been working closely to unravel the unique properties of semiconducting as well as metallic carbon nanotubes. In the next few sections, we will provide an introduction to car-



bon nanotube electronics. We will discuss the bandstructure and the density of states, and provide insights to the fundamental transport mechanisms of the carbon nanotube field effect transistors (CNFETs). We would further discuss the implications these transistors have in terms of circuit performance and look at some of the bottlenecks and challenges in the development of CNT based VLSI design. Instead of delving into the carbon nanotube properties from a physicist’s point of view, we would concentrate on the potentials that these novel devices hold for circuit and VLSI designers.

Bandstructure and Density of States To understand the properties of a device structure it is essential to have a clear understanding of its energy-band structure. Before calculating the E-k (energy vs. wave vector) relation of a carbon nanotube, it is only prudent to understand the bandstructure of graphene [13]. Carbon nanotubes are sheets of graphene and the simplest way to calculate their bandstructure would be to quantize the graphene E-k along the circumference. Let us consider a sheet of graphene where the carbon atoms are packed in a regular hexagonal structure with a C-C bond length acc (∼0.142nm) and a C-C bond energy t0 (∼3eV). It can be noted that all the carbon atoms in the graphene lattice do not see an identical environment. Hence two atoms can be lumped together to form a unit cell, as has been illustrated in Figure 1.5. The entire graphene sheet can thus be constructed by translating the unit cell along the linear combinations of the basis vectors, a1 and a2 . Let us define the translation vector as T = ma1 + na2 where m and n are integers. It can be noted from Figure 1.5 that the basis vectors can be expressed in terms of the geometrical parameters as,

a1 a2

√ 3 x ¯+ = a0 2 √ 3 x ¯− = a0 2

 1 y¯ 2  1 y¯ 2


√ where, a0 = 3acc . In graphene, the 2pz orbitals gives rise to π bonds, which determine the electronic properties of graphene. We may also assume that the electrons are tightly bound to the respective atoms and only the wave functions of neighboring atoms overlap to a small extent. This is known as the tight binding approximation. This tight binding approximation applied to the 2pz orbitals of carbon yields the following E-k relationship of graphene. E(k) = ± |t0 |

3 + 2 cos(k.a1 ) + 2 cos(k.a2 ) + 2 cos(k.a3 )



Nanometer Scale Technologies: Device Considerations


Unit Cell

Ky b1 Kx






Figure 1.5. (a) Real Space lattice of Graphene (b) The reciprocal space representation of graphene showing the first Brillouin zone.

where a3 = a1 −a2 . The positive sign in Eq. 1.2 corresponds to the conduction band and the negative sign corresponds to the valence band. It should be noted that the conduction and the valence bands are exact mirror images of each other. For transport properties, this implies identical hole and electron mobilities. Having obtained the real space lattice, it will be beneficial to obtain the lattice vectors in reciprocal space. Let the basis vectors be b1 and b2 , and they satisfy the relations, ai .bj = 2πδij for i, j = 1, 2


where, δij is the Kronecker delta function, being 1 when i=j and 0 otherwise. The electronic properties can be obtained by translating the real space to the k (wave-vector) space also called the reciprocal space. Using the real space vectors we obtain the reciprocal space vectors for graphene, π  y¯ b  a π π x ¯ − y¯ = b a

b1 = b2

x ¯+


√ where a = 3a0 /2 and b = a0 /2. Figure 1.4 shows the reciprocal lattice space. It can be shown that the energy at the three corners of the Brillouin zone (the smallest volume in the reciprocal vector space such that the total reciprocal space is a periodic repetition of this volume) is zero. These corners can be represented in the kx − ky plane as,   π     π 2π , , −π, 0, − 3  3   π, −3 π ,  (1.5) (kx a, ky b) =  −π , π, 3 , −π, 0, − 2π 3 3



It should be noted that the first three are equivalent and the last three are equivalent since they differ by only the reciprocal lattice vector. Hence we have only two distinct valleys given by (0, ±2π/3). Detailed calculations of the graphene sheet show that this tight binding approach works well in the vicinity of the Fermi point. Since it is this region that accounts for electronic transport in semiconductors, Eq. 1.2 would be used in deriving the bandstructure of carbon nanotubes. A carbon nanotube can be visualized as a sheet of graphene rolled up in a direction given by the chiral vector. The chiral vector C is given by, a2 C = mˆ a1 + nˆ


where, aˆ1 and aˆ2 are the unit vectors along a1 a1 and a1 respectively. This chiral vector (m,n) specifies most of the electronic properties of the nanotube as would be evident subsequently. The diameter of the nanotube is given by,  (1.7) d = a0 n2 + m2 + mn and the translation vector is given by, a1 + t2 ˆ a2 T = t1 ˆ


where, 2m + n dR 2n + m = − dR

t1 = t2


and dR is the highest common divisor of (2m+n) and (2n+m). The number of hexagons in a unit cell is given by, 2(m2 + n2 + mn) (1.10) dR Owing to the periodic boundary condition of the carbon nanotube, the following needs to be satisfied, N=

k.C ≡ kx a(m + n) + ky b(m − n) = 2πu


where, u is an integer. It can be observed that Eq. 1.11 represents a series of lines in the kx − ky plane and if (m-n)/3 is an integer then one of these lines pass through (0, ±2π/3). Hence such nanotubes are metallic. This leads to an important conclusion that without accurate control over chirality (as in the present state of the art) one-third of the nanotubes are metallic and not usable for transistor applications.

Nanometer Scale Technologies: Device Considerations


Eq. 1.2 gives the E-k relationship in the entire Brillouin zone of graphene. Using a Taylor series expansion of Eq. 1.2 near a Fermi point, kF and neglecting higher order terms, the E-k relation near the Fermi point is √ 3acc |t0 | |k − kF | E(k) = 2


Based on this linear approximation the E-k relation in graphene and imposing the periodic boundary condition of carbon nanotubes, the band structure of carbon nanotube is obtained as √

3acc |t0 | kc2 − kt2 E(k) = 2


where, kc and kt are the circumferential and tangential components of the k vectors. For metallic nanotubes the minimum value of kc is zero and hence we obtain a linear dispersion relation √ 3acc |t0 | kt E(k) = 2


whereas, for semiconducting carbon nanotubes the minimum value of kc is 2/3d thereby giving √ E(k) =

3acc |t0 |  (2/3d)2 + kc2 2


Since the conduction and the valence band are mirror images for the carbon nanotube, the bandgap is E(k) =

0.8eV 2acc |t0 | ≈ d d


Figure 1.6 shows typical E-k diagrams of one semiconducting and one metallic nanotube.

Carbon Nanotube Field-effect Transistors The principle of carrier transport in carbon nanotubes is of active research in the device community [18, 3, 59, 37, 26, 27, 30, 36, 38, 23, 28]. Both metallic as well as semiconducting nanotubes are being studied experimentally and theoretically. Although the principle transport mechanisms have not yet been established without reasonable doubt, some of the pioneering works in this field have given us insights into the behavior of carbon nanotube based transistors. In the following few sub-sections we would review a few of these results and discuss their implications.





Figure 1.6. (a) E-k diagram of a semiconducting carbon nanotube (b) E-k diagram of a metallic carbon nanotube. Note: k has been normalized with respect to the maximum value of k (kmax ).

Figure 1.7. (a) Band diagram of a Schottky barrier carbon nanotube with VG >0. Note that the barrier seen by electrons is thin and nearly transparent (b) The band diagram of the same Schottky barrier carbon nanotube with VG
Nanometer Scale Technologies: Device Considerations


Since it was experimentally Schottky Barrier Carbon Nanotube FETs. shown that semiconducting carbon nanotubes (CNTs) can work as channel material of field-effect transistors (FET) [30], significant progress has been made in understanding and modeling the principle transport properties of these transistors.[59] With ultra thin gate dielectrics, low voltage operation of carbon nanotube based transistors were demonstrated [3]. In some of the pioneering work done in IBM research [59], it was observed that the contact plays an important role in determining the performance of these nanotransistors. It has been predicted that in metallic source-drain carbon nanotube transistors, a potential barrier exists between the source/drain and the channel. The current in these devices is determined by the amount of tunneling through this potential barrier, which is modulated by the gate voltage. Numerical study of such Schottky barrier carbon nanotube FETs has been carried out by Heinze et. al. [30] and this has been furthered to include a self consistent solution of Poisson’s equation and ballistic transport mechanism by Guo et. al. [28]. Numerical results demonstrate a clear ambipolar current behavior of Schottky barrier carbon nanotube transistors. The band diagram of the Schottky barrier transistor has been illustrated in Figure 1.7 for positive and negative gate voltages and the physical diagram is illustrated in Figure 1.8a. It can be noted that for positive gate voltages there is electron current and for negative drain voltages a strong hole current is established. The minimal leakage current in Figure 1.8b can be estimated by noticing that it occurs when the electron and hole currents are equal. The tunneling barrier for holes at the drain end is nearly transparent when the gate oxide is thin, thus the off-current for holes is limited by thermionic emission over the barrier, , in the bulk body. The total current of these devices is minimum when the electron current and the hole current are equal to each other. Equal barrier heights for electrons and holes are required to produce the same current, therefore, the barrier heights are . By adding the thermionic emission currents for holes and electrons, we find the minimal leakage current as I∼

Eg − eVD 8ekB T × exp(− ) h 2kB T


in the non-degenerate limit. (Here is Planck’s constant. kB in Boltzman constant and T is the temperature.) Eq. 1.17 can be interpreted in the following way. At equilibrium, the largest barrier height that limits electron and hole current is one half of the band gap, and it decreases by an amount of after the drain voltage is applied. For equal barrier heights of electrons and holes (mid-gap source and drain materials) the minimum drain current occurs when the gate voltage is equal to half the drain voltage, as illustrated in Figure 1.8. Two important aspects of these nanotube transistors are worth mentioning. First, the energy barrier at the Schottky barrier severely limits the transconductance of the nanotube transistors in the ‘ON’ state and reduces the current




Intrinsic CNT


ZrO 2

G (b)


Figure 1.8. (a) A Schottky barrier carbon nanotube FET. Note that the Source and Drain are metallic and a high K dielectric has been used (b) The ID − VG characteristics of the Schottky barrier FET showing ambipolar conduction.



Figure 1.9. (a) A MOSFET like carbon nanotube FET having n+ source and drain regions (b) The ID − VD characteristics of the MOSFET like device showing a higher ‘on’ current than a corresponding Scottky barrier device (for different source drain metal work-functions).

Nanometer Scale Technologies: Device Considerations


Figure 1.10. 1D electrostatics of a carbon nanotube FET showing the oxide capacitance (COX ) and the semiconductor capacitance (Csemi )

delivery capability- a key metric to transistor performance. Second, Schottky barrier CNFETs exhibit strong ambipolar characteristics and this constraints the use of these transistors in conventional CMOS logic families. Some of the design issues with these transistors would be subsequently visited.

Ideal MOSFET-like Carbon Nanotube FETs. To overcome these handicaps associated with the Schottky barrier CNFETs, there have been attempts to develop CNFETs, which would behave like normal MOSFETs (Figure 1.9) [18]. In this MOSFET-like device (refer to Figure 1.9 the un-gated portion (source and drain regions) is heavily doped [27, 38] and it operates on the principle of barrier height modulation by application of the gate potential. It should, however, be noted that that doping in carbon nanotubes is not substitutional doping as in Silicon. The required doping of the source/drain extension may be achieved either chemically or electrically. Carbon nanotubes are intrinsically p-type. With deposition of highly electropositive materials like potassium on a carbon nanotube, Fermi level inside the nanotube can be shifted causing it to behave like n-type. In this case, the on-current is limited by the amount of charge that can be induced in the channel by the gate. It is obvious that the MOSFET-like device will give a higher on current and hence would define the upper limit of performance [18]. Recent experiments have demonstrated that the CNFET can typically be used in the MOSFET-like mode of operation with near ballistic transport [36]. Although the feasibility of MOSFET-like carbon nanotube transistors is questionable, some of the numerical studies have caught the fancy of circuit designers. Guo et al. [18] were the first to predict performance parameters of ideal MOSFET-like carbon nanotube transistors. These



MOSFET-like CNFETs suppress the ambipolar conduction that occurs in SB CNFETs. They also extend the channel length scaling limit because the density of metal-induced-gap-states is significantly reduced. A MOSFET like CNFET has a negative Schottky barrier in the ‘ON’ state and hence delivers more current than a Schottky barrier limited transistor. This has been illustrated in Figure 1.9 where ballistic transport has been assumed in both the devices. Also, the parasitic capacitance between the source and gate electrode is reduced in the MOSFET-like devices, which allows faster operation. MOSFET-like CNFETs will also display a leakage current in the off-state, but that leakage current will be controlled by the full band gap of CNTs and by band to band tunneling.

Charge on a Carbon Nanotube and its Intrinsic Capacitance. So far in our discussion on the carbon nanotube FETs, we have investigated the IV characteristics of the device in the Schottky barrier and the MOSFET-like modes of operation. For circuit design, the extrinsic as well as the intrinsic capacitances need detailed understanding [26]. Figure 1.10 demonstrates the intrinsic capacitances (with 1D electrostatics) of the device, where Cox is the oxide capacitance, Csemi is the semiconducting capacitance. It is a well known theory that for Silicon MOSFETs in the inversion region of operation, the inversion layer is limited to a very narrow width and the semiconducting capacitance is way larger than the oxide capacitance. In carbon nanotubes however, this assumption does not hold and even under inversion, the surface potential, ψs s is strongly modulated by the gate voltage. This results in a semiconducting capacitance that is comparable or even less than the oxide capacitance and the charge (on the channel) is strongly modulated by the gate potential. Principle Scattering Mechanisms. For nanoelectronic applications of carbon nanotube transistors, it is essential to identify the nature of transport and the principle scattering mechanisms. Scattering determines not only the current through the device but also the locations of power dissipation in the nanotube transistor [16]. A single nanotube should provide an ideal conductance of 4e2 /h but in practice a much lower value is typically observed. The anomaly can be attributed to the scattering effects and the imperfections in the contacts. Yao et al. [61] have demonstrated a current handling capacity of 25µA at high biases for metallic carbon nanotubes due to electron backscattering from optical or zone boundary phonons. In more recent experimental data [39] electron-phonon interactions in single walled CNTs have been studied both in the high bias as well as the low bias regimes. It has been observed that for low biases (<∼0.1V), channel lengths less than 200nm has a bias independent conductance, one of the hallmarks of ballistic transport. However for longer channel lengths at low biases, a length dependant conductance has been observed. This has been illustrated in Figure 1.11. In low bias regime, the

Nanometer Scale Technologies: Device Considerations


principle scattering mechanism is due to electronic interactions with acoustic phonons and the corresponding mean free path (mfp) of acoustic phonons has been predicted to be 1.6µm. However at high bias (>0.16V) optical or zone boundary phonons (mfp ∼ 10nm) become relevant and channel lengths less than 100nm shows significant scattering effects. Several other experimental results have been reported in recent publications and with high quality chemical vapor deposition (CVD) materials and ohmic contact strategies, several groups have observed ballistic electron transport in metallic nanotubes [41] and more recently, in semiconducting SWNTs by Javey et al.[35]. Numerical studies of metallic nanotubes have been extensively carried out [34] and the mfp for acoustic phonon scattering has been estimated to be lap ∼ 300nm, and that for optical phonon scattering is lop 15 nm. Transport through these short macromolecular (∼ 10 nm) nanotubes has been shown to be free of significant acoustic and optical phonon scattering and thus essentially ballistic at both high and low voltage limits. From a circuit designer’s point of view, ballistic transport through a semiconducting carbon nanotube FET would imply greater ‘ON’ current and faster speed of operation. The current would be governed by the well-known transport equation for 1D carriers, 4ekB T [ln(1 + exp(ξS )) − ln(1 + exp(ξD ))] (1.18) h where, ξS and ξD are the source-channel and drain-channel potential barriers. Several circuit simulations in this ideal performance limit incorporating the intrinsic capacitance of the CNFETs have been presented in [8, 7, 49]. These results show several terahertz of performance of these nanotransistors. However, the ballistic nature of transport is under close scrutiny and with increasing perfection of the fabrication process, ballistic transport for low voltage applications seem plausible. ID =

Circuit Design and Circuit Compatible Modeling Along with extensive experimental results that are being published and corresponding numerical simulations of these carbon nanotube devices, circuit designers and VLSI experts have started to gauge the performance of carbon nanotubes in digital and analog circuits [8, 7, 49]. Three stage ring oscillators with an oscillation frequency of 220Hz have been demonstrated in [38] (refer to Figure 1.12). Although 220 Hz is indeed a low frequency of operation compared to the terahertz performance predictions, this was one of the first attempts to reveal ac measurements of CNFETs. Simple logic gates and inverters have been experimentally demonstrated by the leading experimentalists [3] and has been illustrated in Figure 1.13. More recent RF measurements [23] have shown performances upto 250MHz thereby confirming the high frequency nature of the



Figure 1.11. The experimentally measured I-V characteristics of a 1.8nm diameter metallic carbon nanotube [39]. Note that for high biases the current saturates showing clear evidence of increased scattering events at high biases.

Figure 1.12. A three stage ring oscillator made out of carbon nanotube FETs. The frequency of operation is about 220Hz [38] and this is limited by the parasitic capacitances of the device geometry and the measuring instruments.


Nanometer Scale Technologies: Device Considerations



Figure 1.13. Logic gates implemented using carbon nanotube FETs. Experimental data [3] showing transfer characteristics of (a) an inverter (b) a latch.

CNTs (refer to Figure 1.14). Till now, all the high frequency measurements are limited by the parasitic capacitances and the low current drive of the individual CNTs. The integration of materials having a high dielectric constant (high-κ) into carbon-nanotube transistors further promises to push the performance limit for molecular electronics [36]. The p-type transistors with subthreshold swings of S ∼ 70 mV per decade and n type transistors exhibiting S ∼ 90 mV per decade have been experimentally demonstrated. High voltage gains of up to 60 have been obtained for complementary nanotube based inverters. The high κ dielectrics like ZrO2 are chemically benign to carbon nanotubes. Further, since all the bonds of carbon are satisfied in a highly symmetric nanotube structure, there is no dangling bond (unlike Silicon) at the oxide-nanotube interface and this ensures absence of trapped charge at the interface. More recently, monolithic complementary logic integrated circuit using carbon nanotubes have been successfully demonstrated thereby opening up possibilities and challenges for a nano-scaled VLSI era. From a simulation point of view modeling of the carbon nanotubes have been attempted for circuit simulations and power/performance metrics of these nanodevices are being studied. In the next two sub-sections we would provide a brief introduction to RF and digital circuit simulation compatible models for CNTs.

An RF Circuit Model of Metallic Carbon Nanotubes. A carbon nanotube, because of its band structure has two propagating channels [8]. To add to this, there is spin up and spin down that results in four channels in the LandauerBüttiker formalism [7]. Based on the Lüttinger liquid theory for a 1D electron gas [7] spin charge separation can be considered for each of the modes of



Figure 1.14. One of the pioneering efforts in measuring RF characteristics of carbon nanotube FETs. Note that the limit 250MHz comes from the parasistic capacitors and not the carbon nanotube itself [23]. Researchers are working on improved methodologies to measure GHz performance of carbon nanotube FETs. Physics poses no restriction on high frequency operation of these nano-devices.

propagation. Consequently these modes can be decoupled and each of them can be modeled as a transmission line (refer to Figure 1.15). The principle circuit elements of the transmission line model incorporate an accurate model of the capacitance and the inductance. For a CNT of diameter d placed on a dielectric of thickness h (backplane connected to ground), the electrostatic capacitance comes out to be CE =

2π cosh−1 (2h/d)


which for typical experimental setups is in the order of tens of aF/µm. To add to this, the quantum capacitance in carbon nanotubes is of considerable significance. The quantum capacitance can be expressed as [8] CQ =

2e vF


where, vF is the Fermi velocity of electrons in the CNT. Numerically CQ comes out to be 100aF/µm proving thereby that both electrostatic as well as the quantum capacitances play pivotal role in the CNTs. The inductance of a CNT comprises of a series connection of of the kinetic inductance and the magnetic inductance. The kinetic inductance can be expressed as,


Nanometer Scale Technologies: Device Considerations

Figure 1.15. A simple transmission line RF circuit model for metallic carbon nanotubes. The contact resistances are the quantum resistances (assuming ballistic transport at dc). CQ represents the quantum capacitance and CES represents the electrostatic capacitance. LK represents the magnetic inductance. CQ and LK are divided by four to account for the spin-charge separation. The magnetic inductance (which is much smaller than the kinetic inductance) has been neglected.



Figure 1.16. The real and imaginary parts of impedance for two different values of g. ‘g’ is the ratio of the semiconducting to the quantum capacitances.

LK =

h 2e2 vF


and numerically it turns out to be 16nH/µm. This is larger than the magnetic inductance of CNTs, the latter being numerically in the order of pF/µm. Thus in nanoscaled transmission line model of the CNTs, the quantum capacitance



and the kinetic inductances have to be incorporated and they would determine the impedance of the transmission line. Figure 1.16 [8] shows the real and the imaginary impedances of the transmission line model for CNTs. However, the damping resistance of a CNT in the quasi-static limit would be around 4e2 /h which would give rise to an over damped impedance response. This RF circuit model has been a classic approach in predicting high frequency behavior of CNTs.

Spice Compatible Model of CNFETs in the Ballistic Performance Limit. Attempts have been made to incorporate CNFETs in a circuit simulation (SPICE) environment by proper modeling of the current-voltage and the capacitance-voltage relations. One such methodology to model ballistic CNFETs has been discussed extensively in [49]. The circuit compatible model of the CNFET has been illustrated in Figure 1.17. The current source IDS is a non-linear current source and the capacitances CGS and CGD are non linear capacitances governed by the piecewise model as, AL exp(ξi ) for ξi < 0 & VGS ≤ ∆1 (1.22) KT AL = qN0 exp(ξi )(1 − α) for ξi < 0 & VGS ≥ ∆1 KT BL for ξi ≥ 0 & VGS ≤ ∆1 = qN0 KT BL (1 − α) for ξi ≥ 0 & VGS ≥ ∆1 = qN0 KT

CGi = qN0

where, i =s,d and L is the length of the nanotube, A,B and α are physical fitting parameters, and 4KT 3πt0 a0


ΨS − ∆1 − µi KT


N0 = ξi =

t0 is the carbon-carbon (C-C) bonding energy (≈ 3eV), a0 the C-C bonding distance (≈ 0.142nm), ∆1 is half the band-gap of the CNFET, ΨS is the surface potential and µS and µd are the source and the drain Fermi-levels respectively. The current Ids is given by the Eq. 1.18. Figure 1.17 illustrates the match between this circuit compatible model and a detailed atmistic numerical simulation. Simulations have also been carried out with ideal CNFET based logic gates and ripple carry adders [49] (where, all extrinsic parasitic capacitances have been neglected).


Nanometer Scale Technologies: Device Considerations

Drain C GD




Gate VFB


Rs Source



Figure 1.17. (a) The proposed compact model for ballistic CNFETs (b) The ID − VG characteristics of a CNFET showing a close match between numerical simulations and the proposed model.

Carbon nanotubes have thus attracted the fancy of physicists, device engineers and circuit designers. Research has begun to harness the potential of these nano devices and use carbon nanotube based transistors in integrated circuit design for the future generations. Although our understanding of these devices needs to be furthered and a considerable portion of the theoretical work has not yet been demonstrated in experiments, the promise is enormous. Like any other device that is in its premature state, reliable production of these devices is definitely an issue and an enormous amount of research is necessary to build CNFETs with performances matrices comparable to the modern day Silicon MOSFETs. However, with their super-scaled dimensions, reliable and high current carrying capabilities and strong mechanical properties, CNTs have emerged as champions among the different revolutionary non-silicon devices that are being explored worldwide.


Molecular Diodes and Switches

Although carbon nanotubes have been the centre of exploratory research as an alternative to Silicon devices, other molecular devices have also gained popularity [50, 2, 44, 12, 10, 47, 42]. The simplest molecular electronic component: one molecule between two metal electrodes: has recently been demonstrated by several groups, leading to diverse charge transport behavior including gaps in conduction [50], Coulomb blockade [2], current rectification [44], bistable switching [12], negative differential resistance (NDR) [25], and Kondo reso-














(c) (d) Figure 1.18. NDR effects in styrene (a) and TEMPO (b) [25]. DRAM cell with molecular RTDs (c) the circuit schematic and (d) the I-V characteristics.

nance [10, 47]. Although the choice of molecule plays a critical role in the operation of metal-molecule-metal junctions, the interface between the molecule and the electrodes has come under increasing scrutiny due to limited agreement between experimental and theoretical analyses. The apparent importance of the contacts in molecular electronic devices suggests that alternative electrode materials may lead to unique charge transport phenomena. For example, recent results show that self-assembled organic monolayers on Silicon lead to current rectification. Recently, styrene and 2,2,6,6-tetramethyl-1-piperidinyloxy (TEMPO) have been shown to have Negative Differential Resistance (NDR) when connected between metal (Au) on one hand and Silicon on the other [25]. This provides concrete motivation for an integration of molecular devices with nanoscaled Silicon. Figure 1.18 illustrate the NDR effect when styrene is in contact with n+ Silicon and TEMPO is in contact with p+ Silicon. At a bias voltage of around 2.5 V, both the molecules exhibit distinct NDR effects. This can be utilized in a number of ways, the most popular being to reduce the refresh rate of DRAMs.


Nanometer Scale Technologies: Device Considerations

The circuit configuration is shown in Figure 1.18. The two NDR devices have been shown as D1 and D2 . The load lines are shown in Figure 1.18. The output voltage VO represents the voltage at the node where the logic value is stored. As the Si MOSFETs are becoming leakier, the output node VO loses charge through the MOSFET. However, in such a situation D1 starts conducting and replenishes the lost charge. The output voltages VO1 , VO2 , and VO3 are the three operating points; however only VO1 and VO2 are stable. Thus the output can be either at a high potential or at a low potential thereby representing two distinct logic values. From a higher level of abstraction, it results in reduced refresh rate for DRAMs, thereby reducing total dissipated power. There have been also attempts to demonstrate multivalued logic operation using organic molecules, build nano-sensors using DNA and perform logic operation using quantum dots, but they will not be discussed in this chapter. The intent is only to provide an introduction to the world of novel devices and applications that are still in the physicists’ and chemists’ laboratory but might find a place in the circuit designers’ standard cell library in the new era of nanotechnology.



This chapter discusses the principle bottlenecks to further scale bulk Silicon devices and provides an introduction to the non-Silicon alternatives for future technologies. It is, by no means, an exhaustive survey of all the novel devices that are being extensively studied, but is principally an attempt to make bring them within the circuit designers’ horizon. The physical properties of carbon nanotubes and fundamentals of carbon nanotube circuit design have been discussed. With the need for higher and higher integration density and complex on-chip functionality, the laws of physics would be taken to their limits and circuit and system designers; would have an increasing important role to play. Understanding the principles of operation of such ultra-scaled devices and using them in the ICs of the future generation would be a hurdle that the device, circuit and the architecture communities have to overcome together.

References [1] 2001 international http://public.itrs.net/.





[2] R.P. Andres, T. Bein, M. Dorogi, S. Feng, J.I. Henderson, C.P. Kubiak, W. Mahoney, R.G. Osifchin, and R. Reifenberger. Science, 272:1323– 1325, 1996. [3] A. Bachtold, P. Hadley, T. Nakanishi, and C. Dekker. Logic circuits with carbon nanotube transistors. Science, 294:1317–1320, 2001.



[4] R. H. Baughman, A. A. Zakhidov, and W. A. de Heer. Carbon nanotubesthe route toward applications. Science, 297:787, 2002. [5] S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De. Parameter variations and impact on circuits and microarchitecture. In Proceedings of Design Automation Conference, pages 338–342, June 2003. [6] J. Brews. High Speed Semiconductor Devices. John Wiley & Sons, New York, 1990. [7] P.J. Burke. Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes. IEEE Transactions on Nanotechnology, 1(3):129–144, September 2002. [8] P.J. Burke. An RF circuit model for carbon nanotubes. IEEE Trans Nanotechnology, 2(1):55–58, March 2003. [9] K. Cao, W.-C.Lee, W.Liu, X.Jin, P.Su, S. Fung, J. An, B.Yu, and C. Hu. Bsim4 gate leakage model including source drain partiotion. IEDM Technical Digest. Electron Devices Meeting, 2000. [10] J. Chen, M.A. Reed, A.M. Rawlett, and J.M. Tour. Science, 286:1550– 1552, 1999. [11] T. Chen and S. Naffziger. Comparison of adaptive body bias (abb) and adaptive supply voltage (asv) for improving delay and leakage under the presence of process variation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(5):888–899, October 2003. [12] C.P. Collier, G. Mattersteig, E.W. Young, Y. Luo, K. Beverly, J. Sampaio, F.M. Raymo, J.F. Stoddart, and J.R. Heath. Science, 289:1172–1175, 2000. [13] S. Datta. Quantum transport: from Atom to Transistor. Cambridge Unievrsity Press, 2003. [14] V. De and S. Borkar. Technology and design challenges for low power and high performance. In Proc. of Intl. Symp. on Low Power Electronics and Design, pages 163–168, August 1999. [15] R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc. Design of ion-implanted MOSFETs with very small physical dimensions. IEEE J. Solid-State Circuits, 1974. [16] M. Dresselhaus, G. Dresselhaus, and P. Avouris. Carbon Nanotubes: Synthesis, Structure, Properties, and Applications. Springer-Verlag, New York, 2001. [17] M. Dresselhaus, G. Dresselhaus, and P. Eklund. Science of Fullerenes and Carbon Nanotubes. Academic Press, New York, 1996. [18] J. Guo et. al. Assessment of silicon mos and carbon nanotube fet performance limits using a general theory of ballistic transistors. Technical Digest IEDM, 2002.

Nanometer Scale Technologies: Device Considerations


[19] K. Bowman et. al. Impact of die-to-die and within die parameter fluctuations on the clock frequency distribution in gigascale integration. Journal of Solid State Circuits, 37:183–190, 2002. [20] Lo et. al. Modeling and characterization of N/sup +/- and P/sup +/polysilicon-gated ultra thin oxides (21-26 /spl aring/). Symposium on VLSI Technology, 1997. [21] R. Dennard et al. Design of ion-implanted mosfet’s with very small physical dimensions. IEEE J. Solid State Ckt., page 256, October 1974. [22] Vivek De et. al. Techniques for leakage power reduction. IEEE Press, Piscataway NJ, 2000. [23] D.J. Frank and J. Appenzeller. High-frequency response in carbon nanotube field-effect transistors. Electron Device Letters, 25(1):34–36, January 2004. [24] A.S. Grove. Physics and Technology of Semiconductor Devices. John Wiley & Sons, 1967. [25] Nathan P. Guisinger, Mark E. Greene, Rajiv Basu, Andrew S. Baluch, and Mark C. Hersam. Room temperature negative differential resistance through individual organic molecules on silicon surfaces. Nano Lett., 4(1):55–59, 2004. [26] J. Guo, S. Goasguen, M. Lundstrom, and S. Datta. Metal-insulatorsemiconductor electrostatics of carbon nanotubes. Appl. Phys. Lett., 81:1486, 2002. [27] J. Guo, M. Lundstrom, and S. Datta. Performance projections for ballistic carbon nanotube field-effect transistors. Appl. Phys. Lett., 80:3192, 2002. [28] S. Guo, S. Datta, and M. Lundstrom. A numerical study of scaling issues for schottky barrier carbon nanotube transistors. IEEE Transactions on Electron Devices, 51:172, February 2004. [29] F. Hamzaoglu and M. Stan. Circuit-level techniques to control gate leakage for sub-100 nm cmos. International Symposium on Low Power Design, 2002. [30] S. Heinze, J. Tersoff, R. Martel, V. Derycke, J. Appenzeller, and Ph. Avouris. Carbon nanotubes as schottky barrier transistors. Phys. Rev. Lett., 89:106801, 2002. [31] S. Iijima. Helical microtubules of graphitic carbon. Nature, 354:56, 1991. [32] S. Iijima and T. Ichilashi. Single-shell carbon nanotube of 1nm diameter. Nature, 363:603–605, 1993. [33] J. Jacobs and D. Antoniadis. Channel profile engineering for mosfet’s with 100 nm channel lengths. IEEE Transactions on Electron Devices, 42:870–875, May 1995.



[34] A. Javey, J. Guo, M. Paulsson, Q. Wang, D. Mann, M. Lundstrom, and H. Dai. High-field, quasi-ballistic transport in short carbon nanotubes. Physical Review Letters, 92:106804, 2004. [35] A. Javey, J. Guo, and Q. Wang. Nanotechnology: A barrier falls. Nature, 424:654, 2003. [36] A. Javey, H. Kim, M. Brink, Q. Wang, A. Ural, J. Guo, P. McIntyre, P. McEuen, M. Lundstrom, and H. Dai. High dielectrics for advanced carbon nanotube transistors and logic. Nature Materials, 1:241, 2002. [37] A. Javey, Q. Wang, A. Ural, Y. Li, and H. Dai. Carbon nanotube transistor arrays for multi-stage complementary logic and ring oscillators. Nano Lett., 2:929–932, 2002. [38] A. Javey, Q. Wang, A. Ural, Y. Li, and H. Dai. Carbon nanotube transistor arrays for multi-stage complementary logic and ring oscillators. Nano Lett. 2, pages 929–932, 2002. [39] Ji-Yong, Sami Rosenblatt, Yuval Yaish, Vera Sazonova, Hande Üstünel, Stephan Braig, T. A. Arias, Piet W. Brouwer, and Paul L. McEuen. Electron-phonon scattering in metallic single-walled carbon nanotubes. cond-mat/0309641, September 2003. [40] Keshavarzi, K. Roy, , and C. F. Hawkins. Intrinsic leakage in low power deep submicron cmos ics. Int. Test Conf., pages 146–155, 1997. [41] W. Liang, M. Bockrath, and D. Bozovic. Nature, 411:665, 2001. [42] W. Liang, M.P. Shores, M. Bockrath, J.R. Long, and H. Park. Nature, 417:725–729, 2002. [43] C. Mead. Scaling of MOS technology to submicrometer feature sizes. Analog Integ. Ckt. and Signal Process., 6:9–25, 1994. [44] R.M. Metzger and J. Mater. Chem., 10:55–62, 2000. [45] S. Mukhopadhyay, C. Neau, R.T. Cakici, A. Agarwal, C.H. Kim, and K. Roy. Gate leakage reduction for scaled devices using transistor stacking. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 11(4), August 2003. [46] S. Mukhopadhyay and K. Roy. Modeling and estimation of total leakage current in nano-scaled-CMOS devices considering the effect of parameter variation. In Proceedings of the 2003 International Symposium on ISLPED ’03., pages 172–175, Aug 2003. [47] J. Park, A.N. Pasupathy, J.I. Goldsmith, C. Chang, Y. Yaish, J.R. Petta, M. Rinkoski, J.P. Sethna, H.D. Abruna, P.L. McEuen, and D.C. Ralph. Nature, 417:722–725, 2002. [48] R. Pierret. Semiconductor Device Fundamentals. Addison-Wesley, MA, 1996.

Nanometer Scale Technologies: Device Considerations


[49] A. Raychowdhury, S. Makhopadhya, and K. Roy. Modeling of ballistic carbon nanotube field effect transistors for efficient circuit simulation. International Conference on Computer Aided Design, pages 487–490, November 2003. [50] M.A. Reed, C. Zhou, J. Muller T.P. Burgin, and J.M. Tour. Science, 278:252–254, 1997. [51] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. In Proceedings of the IEEE, volume 91, Feb 2003. [52] K. Roy and S. C. Prasad. Wiley Interscience Publications, New York, 2000. [53] G. Sery. Life in CMOS: Why chase life after that. Proceeding of Design Automation Conference, pages 78–83, June 2002. [54] Y. Taur. CMOS Scaling and Issues in sub-0.25?m Systems. IEEE Press, Piscataway NJ, 2000. [55] Y. Taur and T. H. Ning. Fundamentals of Modern VLSI Devices. Cambridge University Press, New York, 1998. [56] Thompson, P. Packan, , and M. Bohr. Linear versus saturated drive current: tradeoffs in super steep retrograde well engineering. Symposium on VLSI Technology, pages 154–155, 1996. [57] S. Thompson, P. Packan, and M. Bohr. MOS scaling: Transistor challenges for the 21st century. Intel Technology Journal, 1998. [58] S. Venkatesan, J.W. Lutze, C. Lage, and W.J. Taylor. Device drive current degradation observed with retrograde channel profiles. International Electron Devices Meeting, pages 419–422, 1995. [59] S. Wind, J. Appenzeller, R. Martel, V. Derycke, and P. Avouris. Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes. Appl. Phys. Lett., 80:3817–3819, 2002. [60] N. Yang, W. Henson, and J. Hauser. Modelling study of ultrathin gate oxides using tunneling current and capacitance-voltage measurement in mos devices. IEEE Trans On Elec Dev, 46(7), july 1999. [61] Z. Yao, C. L. Kane, and C. Dekker. High-field electrical transport in single-wall carbon nanotubes. Phys. Rev. Lett., 84:2941–2494, 2000.

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In his famous book from 1956, "Probabilistic Logics and the Synthesis of Reliable Organisms from Unreliable Components", John von Neumann had talked about building reliable computing systems from fault-prone components. Historically at that point in time, it made perfect sense. The valves that were used as switching devices at that time used to burn out frequently, and hence the ability to maintain reliability in the presence of such possibilities was very important. However, with the advent of silicon transistors, and with the increasing perfection of semiconductor manufacturing, for decades, this work was of lesser importance. Of course, fault-tolerant computing has always been a major research area, especially for mission critical systems. Nevertheless, the idea of designing systems assuming non-zero defect probabilities in the substrate, has not been common until recently, as researchers consider the use of nanotechnology based devices as switching elements. In current semiconductor manufacturing processes, immediately after a silicon wafer is fabricated, tests are carried out and defective parts are rejected. Manufacturing yield is determined by the percentage of parts that come out without defects. Unfortunately, with silicon-based devices scaled down to a few nanometers, or even newer technologies (such as molecular self-assembled substrates, quantum dot cellular automata type devices, or carbon nanotube based switches), the defect probability will be quite high. As a result, throwing away parts that contain any defect at all will not be an option. Instead, robust systems will have to be designed using these fault-prone substrates. As a result, the notion of defect-tolerance will be a prime force in design. Instead of computing manufacturing yield in the present manner, parts will likely be graded according to their reliability characterizations. With this in mind, researchers have already started looking into defecttolerant computing. There are two major schools of thoughts in defecttolerance. One is based on reconfigurability, and often self-reconfigurability of systems. Such systems are designed to diagnose and map their own fault locations, and reconfigure the computing around the faulty regions, so as to provide reliable results. The other strain of research is based on probabilistic characterization of the faulty substrates. Redundancy based defect-tolerance is 37 S.K. Shukla and R.I. Bahar (eds.), Nano, Quantum and Molecular Computing, 37-38. © 2004 Kluwer Academic Publishers. Printed in the Netherlands.



then designed into the system in order to guarantee a certain level of reliability given the particular characterization of the faults. In this part of the book, we present six chapters. The first two focus mainly on fault detection and reconfigurability-based defect tolerance. The last four are based on defect-tolerance through probabilistic assumptions. Due to the very nature of the computation at the nano-scopic level, new models of computation — distinguishable from Boolean logic — may actually help in understanding the interaction between quantum phenomena and valid computation. In particular, Chapter 5 in this part presents one such model of computation that takes into account thermal energy and information theoretic bounds on energy expenditure in bit transformations. In addition, the final chapter in this section takes a statistical view of computing with quantum devices, and draws contrast against current silicon technologies. We believe this part of the book will provide the readers with an interesting sampling of defect-tolerance work pertaining to nanotechnology. Also included in these chapters is discussion regarding the corresponding design automation problems and emerging tools and techniques needed to support these defecttolerant systems.

Chapter 2 NANOCOMPUTING IN THE PRESENCE OF DEFECTS AND FAULTS: A SURVEY Paul Graham Los Alamos National Laboratory Los Alamos, NM, USA [email protected]

Maya Gokhale Los Alamos National Laboratory Los Alamos, NM, USA [email protected]


Computing systems implemented with nanotechnology will need to employ defect- and fault-tolerant measures to improve their reliability due to the large number of factors that may lead to imperfect device fabrication as well as the increased susceptibility to environmentally induced faults when using nanometerscale devices. Researchers have approached this problem of reliability from many angles and this survey will discuss many promising examples, ranging from classical fault-tolerant techniques to approaches specific to nanocomputing. The research results summarized here also suggest that many useful, yet strikingly different solutions may exist for tolerating defects and faults within nanocomputing systems. Also included in the survey are a number of software tools useful for quantifying the reliability of nanocomputing systems in the presence of defects and faults.


nanocomputing, redundancy, fault, defect, fault tolerance, defect tolerance

Introduction With the increasing fabrication costs of CMOS-based computing devices and the ever-approaching physical limits of their fabrication and use, a significant community of researchers are exploring a number of nanometer-scale 39 S.K. Shukla and R.I. Bahar (eds.), Nano, Quantum and Molecular Computing, 39-72. © 2004 Kluwer Academic Publishers. Printed in the Netherlands.



alternatives to existing CMOS silicon technology. Devices and architectures of interest include carbon nanotubes[34], single-electron transistors (SETs)[29], quantum-dot cellular automata (QCA)[47], molecular devices[48], and quantum computing (see Chapter 8), to name just a few. With this demand to use nano-scale devices to create more powerful and complex computers, a significant concern is the reliability of these devices and the systems built with them. For instance, the chemical processes for building molecular devices will have significantly lower yields than those obtained through current fabrication practice, resulting in aggregates with high defect rates. Since they manipulate single electrons, devices such as QCA and SETs are susceptible to background charge fluctuations that can cause faults during operation. The decrease in the device scales used also means that radiation effects, electromagnetic interference, and power and temperature effects will all be more challenging to counteract. These effects are already being seen: upsets in 150-nm CMOS devices by atmospheric neutrons have already been observed [15]. The large number of factors that will affect the reliability of nanocomputing devices suggests that defect and fault tolerance will be an integral part of device and system design for nanocomputing. In this chapter, we will provide a brief survey of the many techniques and tools being researched to aid in constructing reliable nanocomputers from unreliable nano-scale devices. These techniques range from applications of classical defect- and fault-tolerant techniques to techniques that are unique to nano-scale devices. We will first define key terms and concepts that will be used throughout the paper and the remaining sections will cover classical error masking and reconfiguration techniques (Section 2.2), non-traditional computing models and architectures (Section 2.3), and tools for defect and fault tolerance (Section 2.4). We will conclude the chapter with some general summary comments.



Before surveying current research into reliable nanocomputing, we will define several terms and concepts that will be used throughout the chapter. Additionally, we will provide a framework for discussing the specific ideas being pursued in the nanocomputing community for building reliable systems. A defect, or more specifically, a manufacturing defect is a physical problem with a system that appears as a result of an imperfect fabrication process. By contrast, a fault is an incorrect state of the system due to manufacturing defects, component failures, environmental conditions, or even improper design[46]. Faults can be:

permanent, as in the case of physical defects or permanent device failures during the lifetime of the system;

Nanocomputing in the Presence of Defects and Faults: A Survey


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